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How can I translate L1-cache hit miss rate and element of the number of memory accesses?

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I am new to gem5. I hope to get some advice to use this tool.

After running the simulation of se.py, I got stat.txt.

But when I checked the number of hit and miss, there are a lot of memory accesses which I didn't expect.

What should I do out if I want to know the each memory address for each memory access and L1 cache hit/miss numbers?

My questions are

1. which file should I look at if I want to figure out the element and address of memory accesses ?

2. Is there anyway to set the range of the program to get statistic results from the specific range?

3. Is there anyway to get the L1 data cache miss/hit rate only? (I think the stat.txt shows too many number of miss and hit numbers. So, it means it counts other memory accesses outside of running the specific program).

Thank you!
asked Oct 3 in Classic Memory by sch8906 (120 points)

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