I am trying to implement the behavior of the ARM Accelerator Coherency Port, which enables an accelerator to be connected directly to the L2 cache of the CPU cluster on an SoC and access data coherently. The expected behavior of ACP for a store initiated by an accelerator is to first snoop all the L1 caches. Any modified lines are written back to L2 and invalidated in the L1 cache, and then the store from the accelerator is allowed to execute.
My accelerator is a SimObject which I've connected to the L2 crossbar. What I want to do ultimately is to make an L1 cache respond to a store snoop by cleaning and evicting its own copy to the L2 cache. I cannot figure out how to accomplish this, however. It seems that a CleanEvict command is only intended to be issued by the cache doing the clean and evict. My current workaround is to use a ReadExReq command to transfer ownership of the appropriate cache line to the accelerator. But this doesn't force a writeback to L2. Is there any existing mechanism in gem5 that lets me accomplish this, or will I need to implement a new command?
I am running gem5 in SE mode with the classic memory model.