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Victim cache problem. Writebacks out of exclusive cache are more than writeback_hits into cache

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I am trying to make victim cache in gem5 that stores only dirty victims coming from L1 data cache. To do this, i have added new cache in gem5 and set it's clusivity parameter to 'mostly exclusive'. I have added this cache between L1D cache and tol2bus (by modifying BASECPU.py, CacheConfig.py, Caches.py). Moreover, i have set WritebackClean parameter of L1D cache as false,so that only dirty blocks can enter victim cache.

Is this correct way to implement victim cache for dirty blocks or some more modification is required.

One problem that i have found in stats file is that writebacks out of this victim cache are more that DirtyWriteback_hits into victim cache. I could not understand its reason.

Because, i think writebacks out of this victim cache should not be greater than DirtyWriteback_hits into victim cache. Victim cache is storing only dirty blocks of LID cache and how blocks going out of  Victim cache can be greater than blocks going into victim cache.

Victim cache parameter are as below

class VCache(Cache):
    assoc = 16
    tag_latency = 1
    read_latency = 1
    write_latency = 1
    response_latency = 1
    enable_bank_model = False
    mshrs = 2
    size = '1kB'
    tgts_per_mshr = 8
    clusivity = 'mostly_excl'
    write_buffers = 8

My .json file is shown below
"vcache": {
                    "cpu_side": {
                        "peer": "system.cpu.tolvbus.master[0]",
                        "role": "SLAVE"
                    "num_banks": 1,
                    "clusivity": "mostly_excl",
                    "prefetcher": null,
                    "system": "system",
                    "enable_bank_model": false,
                    "write_buffers": 8,
                    "response_latency": 1,
                    "cxx_class": "Cache",
                    "size": 1024,
                    "write_latency": 1,
                    "clk_domain": "system.cpu_clk_domain",
                    "max_miss_count": 0,
                    "eventq_index": 0,
                    "default_p_state": "UNDEFINED",
                    "p_state_clk_gate_max": 1000000000000,
                    "mem_side": {
                        "peer": "system.tol2bus.slave[0]",
                        "role": "MASTER"
Can anyone, please find problem in my implementation.

Thanks in advance
asked May 29 in Coding Guidelines by maq.uetian (680 points)

1 Answer

0 votes
Dear All,

                  I found that extra write backs from victim cache are being generated in "recvTimingResp" function in cache.cc. While normal writebacks are generated by "allocateblock" function

                   Can any one find problem in implementation


answered Jun 16 by maq.uetian (680 points)