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Multicore and Manycore in Gem5

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I am new to GEM5 and want to know if I could use GEM5 to simulate a specific problem and measure timing without taking into account the time taken to transfer the data over the interfaces such as SPI or USB.

I want to simulate message passing between different cores. An example topology is given as under

ARM core <---->SPI<----->  ARM/SPARC Core1  <------shared memory----------> ARMSPARC Core2 <--------------------SPI/i2c------->USB2SPI Converter <-------USB------>X86 Processor

I want to know if it is possible to simulate a complete system like this and run code on each of the processor?
Will I be able to pass data between the processing units?  How will be interfaces like SPI and USB be handled?

Thanks & Regards

asked Mar 28 in Configuration by ash32 (120 points)

1 Answer

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Short answer: Not easily.

Longer answer: Parts of this system you can simulate with gem5 today (e.g., ARM cores + shared memory, devices). The things that are not available are:

  1. Detailed SPI/i2c timing models. There *may* be some support for emulation (check the src/dev directory), but even if there are models there they don't have detailed timing of these interconnects.
  2. The above also applies to USB
  3. gem5 currently only supports a single ISA.
The last item will likely be the most work to implement. I believe implementing timing models for SPI/i2c/USB would be pretty straightforward. To implement a system that has multiple ISAs will be much more difficult.
However, it would be a welcome addition to gem5!
answered Mar 28 by powerjg (6,280 points)