Short answer: Not easily.
Longer answer: Parts of this system you can simulate with gem5 today (e.g., ARM cores + shared memory, devices). The things that are not available are:
- Detailed SPI/i2c timing models. There *may* be some support for emulation (check the src/dev directory), but even if there are models there they don't have detailed timing of these interconnects.
- The above also applies to USB
- gem5 currently only supports a single ISA.
The last item will likely be the most work to implement. I believe implementing timing models for SPI/i2c/USB would be pretty straightforward. To implement a system that has multiple ISAs will be much more difficult.
However, it would be a welcome addition to gem5!