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Does gem5 support the AVX gather instruction

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Hi all,

I am new to gem5 and try to do some experiment on the x86 simd extensions. I have got two questions.

1. I know gem5 might not ready for the newest AVX512 instruction set. But does current gem5 support the AVX gather instruction? Where should I go to look for it?

2. I am trying to adding some new instructions using the pseudo-instruction function in gem5. I am wondering does pseudo instruction only work in the full system simulation? Is there any easy way that we can make it work for sys call simulation as well?

Thanks in advance,

asked Mar 20 in x86 by PST (230 points)

1 Answer

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1. gem5 does not have support for most of the SIMD instructions in x86, and definitely does not have any of the AVX instructions implemented.

For AVX instructions. I believe there was recently a patch committed that updated gem5's support for vector registers. This patch was primarily for ARM, but it should be possible to extend for the x86 vector instructions. Implementing the AVX instructions would be great! But it's not something we've found the time to do.

2. Psuedo-insts work in both SE and FS mode. You may need to change a flag in the makefile in util/m5 to not define M5_OP_ADDR (or something like that) to get them to work simply in SE mode.
answered Mar 21 by powerjg (6,280 points)
selected Mar 21 by PST